MOS transistors having lightly doped source and drain extensions are generally made by forming on the surface of a substrate of single crystalline silicon a gate line over a thin layer of silicon oxide. The gate line may be made of doped polycrystalline silicon, a refractory metal, or a refractory metal silicide. The surface of the substrate on each side of the gate line is then lightly doped. A layer of silicon oxide is then deposited, generally by a chemical vapor deposition (CVD) technique, over the lightly doped substrate surface on each side of the gate line and over the gate line. The silicon oxide is then anisotropically etched to removed the silicon oxide layer from the surface of the substrate on each side of the gate line, and from the top surface of the gate line, but leaving a layer of the silicon oxide along each side wall of the gate line. The silicon oxide layer along each side wall of the gate line projects over and covers a portion of the lightly doped substrate surface along leach side of the gate line. The exposed surface of the substrate is then more heavily doped to form the source and drain regions of the transistor having lightly doped extension extending under the silicon oxide layer on the side walls of the gate line.
All CVD silicon oxide exhibits large density of electron and hole states. Although the trap density decreases after the CVD oxide is densified, the trap density in any CVD oxide film is orders of magnitude larger that in a thermally grown silicon oxide film. The drain extension region of N-channel (P-channel) MOS transistors is a lightly doped shallow N- (P-) layer. The resistivity of the N- (P-) layer is relatively large. When an electron (hole) is trapped in the spacer oxide layer which is on the side walls of the gate line and over the drain extension, an electron (hole) is repealed away from the N- (P-) region. As the number of trapped electrons (holes) in the spacer oxide layer is increased, the number of mobile electrons (holes) is reduced. The series resistance of this region increases with the number of electrons (holes) trapped in the spacer sidewall. It has been shown that under certain conditions there is a high lateral electrical field at the source end of the channel of a MOS transistor having a lightly doped drain extension. The hot carrier generation rate at this region is very high. Therefore, electrons (holes) can be trapped at the spacer sidewall oxide of both source and drain lightly doped regions. The drain current and the transconductance of the device is, therefore, degraded as the number of electrons (holes) trapped at the spacer sidewall oxide at the source and drain regions of an N-channel (P-channel) MOS transistor is increased. Thus, the trap state in the spacer oxide at the sidewall of the gate line is known to cause the degradation of the performance of the transistor.